The ModelSim advanced code coverage capabilities provide valuable metrics for systematic verification.
ModelSim’s advanced code coverage capabilities and ease of use lower the barriers for leveraging this valuable verification resource. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF). All user interface operations can be scripted and simulations can run in batch or interactive modes. You can edit, recompile, and re-simulate without leaving the ModelSim environment. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. All windows update automatically following activity in any other window. The graphical user interface is powerful, consistent, and intuitive. Its architecture allows platform-independent compile with the outstanding performance of native compiled code. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity.
